The present invention generally relates to electrical circuits, and more particularly relates to latch circuits for receiving an input signal using a clock signal that is asynchronous to the input signal.
Digital integrated circuits (ICs) generally operate in a synchronous mode. Data is transmitted synchronously within an IC when a clock signal captures the data output by one stage at the input of another stage. Clock signals are distributed all around the various stages and functional units on an IC and, along with signals used to select the intended stage or unit, cause the capturing of the data. Various circuits are used to capture data, such as flip-flops and latches, and even though each operates somewhat differently, they all utilize clock signals to capture data.
Capturing data at the input of a stage within an IC can be easily accomplished as long as a proper relationship between transitions in the clock and data signals is maintained. This proper relationship is usually defined in terms of minimum setup and hold times and can usually be controlled within the IC. However a problem arises when data is transferred between two domains that operate asynchronously with respect to each other. For example an IC may receive an external signal that is asynchronous to the IC""s internal clock signal. Capturing circuits such as flip-flops are unable to capture the external signal when the signal changes during a transition in the clock signal since the signal is in mid-transition. In addition not only is the data not xe2x80x9ccaughtxe2x80x9d or captured correctly at that edge, but additionally the capturing circuit suffers from a xe2x80x9cconfusionxe2x80x9d of sorts. It captures a xe2x80x9cconfusedxe2x80x9d or intermediate mid-point value which is then output to the next stage requiring data. The time it takes for the capturing circuit to become xe2x80x9cunconfusedxe2x80x9d can be statistically determined, but can be in some rare cases quite long. So the problem is not so much that the data is not captured perfectly at the exact earliest edge possible, but that the capturing device can be forced into this confused state . The confused state is known as metastability. Once a flip-flop becomes metastable, its output can take a significant amount of time to correctly transition to a recognizable logic state, and sometimes this logic state is not the correct one. The output signal can take many forms during metastability, such as assuming an intermediate voltage and oscillating for an extended period.
The metastability problem can be avoided within a digital IC or between digital ICs by obeying minimum setup and hold times. Most busses used to communicate data and actions between various ICs are specified so that data is always ready to be input at the input of the next IC or section in time for the next clock, in much the same way that circuits within an IC are designed.
However no known circuit can guarantee the correct operation of a capturing device with a completely unknown external data transition. While some precautions can be taken to reduce the effects of metastability, no known circuit can completely remove it. FIG. 1 illustrates a latch circuit 20 that reduces the effects of metastability known in the prior art, including a buffer 22 and two clocked D-type flip-flops 24 and 26. Flip-flops 24 and 26 are driven by the same clock signal, and the output of the first flip-flop 24, labeled xe2x80x9cQ1xe2x80x9d, feeds the D input of the second flip-flop 26. The output of flip-flop 26, labeled xe2x80x9cQ2xe2x80x9d, forms the output of latch circuit 20. Latch circuit 20 operates under the assumption that a single stage flip-flop will xe2x80x9csettlexe2x80x9d (end its metastability).within a fixed period of time, and thus be stable before the clock of the next stage transitions. Statistically, the relationship between the inherent settling time and the clock rate of the system determines the likelihood of the metastability working its way through the two flip-flops and into the synchronous system. But it does not eliminate the chance of a metastability-induced error.
This phenomenon is better understood with respect to FIG. 2, which illustrates a timing diagram 30 useful in understanding the operation of latch circuit 20 of FIG. 1. In FIG. 2 the horizontal axis represents time and the vertical axis the amplitude, in volts, of several relevant signals. As shown the INPUT signal makes a transition between a logic low value and a logic high value. In order to avoid metastability, the INPUT signal should be settled for at least a setup time labeled xe2x80x9ctSUxe2x80x9d before the rising edge of the CLOCK signal. As shown in FIG. 2 the CLOCK input signal makes a transition just within tSU and metastability results. Thus signal Q1 initially assumes an intermediate value. Alternatively instead of assuming an intermediate value, the metastable state may cause signal Q1xe2x80x2 to oscillate between states before finally resolving to a recognizable logic state. As long as the metastability has ended by the next transition of the CLOCK signal, no ultimate problem will result. Even if the metastable condition resolves to a low level, the high level will be recognized at the input of flip-flop 26 at the following CLOCK signal and the operation of the circuit is not affected by the metastability.
However the decay time of the metastable event is statistically variable and even in latch circuit 20 there is some probability that the metastable state will last long enough to be seen at the input of flip flop 26 and thus reach the output. The probability is related to the CLOCK rate and increases with increases in the CLOCK rate. The fastest rate at which the two flip-flops can be clocked is set by the known statistical decay of the metastable event in flip-flop 24, and this value is not guaranteed for all time. This lack of predictability of the circuit and the remote chance that it could pass a metastable event makes it and other similar circuits less than perfect. An additional flip-flop stage could be added to the output of flip-flop 26 but this additional flip-flop would increase the group delay through latch circuit 20 and may not be tolerable.
Accordingly, it would be desirable to have a latch circuit which is able to provide an output signal as a correct representation of an input signal regardless of when the input signal changes state in relation to a clock signal. These and other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.
A latch circuit with a metastability trap is provided. The latch circuit includes at least three input latches, a first logic gate, a second logic gate, and a flip-flop. The at least three input latches capture values of an input signal at corresponding successive points in time distributed over a predetermined period which is less than half of a fundamental period of the input signal. The first logic gate has a plurality of input terminals coupled to corresponding output terminals of each of the at least three input latches, and an output terminal for providing a first intermediate signal. The first logic gate activates the first intermediate signal in response to signals at all of the plurality of input terminals being in a first logic state, and keeps the first intermediate signal inactive otherwise. The second logic gate has a plurality of input terminals coupled to corresponding output terminals of each of the at least three input latches, and an output terminal for providing a second intermediate signal. The second logic gate activates the second intermediate signal in response to signals at all of the plurality of input terminals being in a second logic state. The second logic gate keeps the second intermediate signal inactive otherwise. The flip-flop has a set input terminal coupled to the output terminal of the second logic gate, a reset terminal coupled to the output terminal of the first logic gate, and an output terminal for providing an output signal of the latch circuit.
A method is also provided for trapping metastability events to provide a metastable-free output signal. At least three successive values of an input signal are latched over a predetermined period which is less than half of a fundamental period of the input signal to provide at least three corresponding latched values. A first intermediate signals is activated when all of the at least three corresponding latched values are in a first logic state. A second intermediate signal is activated when all of the at least three corresponding latched values are in a second logic state. An output signal is placed in a first predetermined logic state in response to the second intermediate signal and is changed from the first predetermined logic state to a second predetermined logic state in response to the first intermediate signal.